1. Field of the Invention
The present invention relates to an interrupt controller for selecting one interrupt request from a plurality of interrupt requests and for generating an interrupt level number representing the priority assigned to the selected interrupt request and an interrupt identification number representing the cause of the selected interrupt request.
2. Description of the Prior Art
In general, most computer systems can control interrupt handling by using two numbers: an interrupt level number and an interrupt identification number. The interrupt level number represents the priority assigned to the interrupt request to be handled or the urgency with which the interruption is to be handled. The interrupt identification number represents the cause of the interruption. Generally, an interrupt controller generates and furnishes such an interrupt level number and an interrupt identification number to a central processing unit or CPU.
Referring now to FIG. 9, there is illustrated a block diagram showing the structure of a prior art interrupt controller. In the figure, reference characters IE10 to IE17 denote interrupt handling elements, A1 to A7 denote interrupt request signals, and S1 to S2 denote three bits of a 3-bit interrupt level number signal, respectively. The 3-bit interrupt level number signal can represent any of eight possible interrupt level numbers 0 through 7 in decimal. When the 3-bit interrupt level number signal represents the number 0, it indicates that there is no interrupt request. On the other hand, when the 3-bit interrupt level number signal represents any of the interrupt level numbers 1 through 7 other than zero, it indicates that there is an interrupt request with the priority corresponding to the value of the 3-bit interrupt level number signal. The interrupt level numbers 1 through 7 indicate priority, with priority increasing in ascending order of the numbers. Reference characters N0 through N2 denote three bits of a 3-bit interrupt identification number signal, respectively. The 3-bit interrupt identification number signal can represent any of eight possible identification numbers 0 through 7 in decimal, which correspond to interrupt request signals A0 through A7, respectively.
Referring next to FIG. 10, there is illustrated a block diagram showing the structure of each of the interrupt handling elements IE10 through IE17. In the figure, reference character CMP denotes a comparator, LR denotes a 3-bit level number register, NR denotes a 3-bit identification number register, SLT denotes a 6-bit selector, and G50 denotes an AND gate. Furthermore, reference character A denotes an interrupt request signal. When the interrupt request signal has a "HIGH" potential or level, it indicates that there is an interrupt request.
As shown in FIG. 11, the comparator CMP is comprised of inverters 11a to 11c, exclusive OR gates 11d and 11e, AND gates 11f through 11j, and OR gates 11k and 11l. When a 3-bit binary number composed of inputs J0 to J2 that lies in the range of 0 to 7 in decimal is greater than another 3-bit binary number composed of other inputs K0 to K2 that lies in the range of 0 to 7 in decimal, the comparator CMP furnishes an output E having a "HIGH" level. The level number register LR as shown in FIG. 10 can furnish a 3-bit output composed of three bits LV0 to LV2, which represents any of the eight possible interrupt level numbers 0 through 7 which is assigned to the interrupt handling element including the level number register LR.
The identification number register NR as shown in FIG. 10 can furnish a 3-bit output composed of three bits CN0 to CN2, which indicates any of eight possible identification numbers 0 through 7 which is assigned to the interrupt handling element including the identification number register NR. When the selector SLT receives an input signal S with a "LOW" potential or level, it can furnish values applied to its terminals T0 to T5 by way of its output terminals Q0 to Q5. On the other hand, when the selector SLT receives an input signal S with a "HIGH" potential or level, it can furnish values applied to its terminals P0 to P5 by way of the output terminals Q0 to Q5. The identification number registers NR of the interrupt handling elements IE0 through IE7 are preset so that they indicate the identification numbers 0 through 7, respectively. The description on a circuit for writing data into the level number register LR and identification number register NR of each interrupt handling element will be omitted hereafter because it is not directly related to the present invention.
Next, a description will be made as to the operation of each of the interrupt handling elements as shown in FIG. 10. The comparator CMP compares the 3-bit output signal composed of the three bits LV0 through LV2 of the level number register LR with a 3-bit input signal composed of three bits IS0 through IS2. If the interrupt level number which is assigned to each of the interrupt handling elements and which is designated by the outputs LV0 through LV2 of the level number register LR is greater than another interrupt level number designated by the inputs IS0 through IS2, the comparator CMP causes its output E to go "HIGH". On the contrary, if the interrupt level number designated by the outputs LV0 through LV2 of the level number register is equal to or less than the other interrupt level number designated by the inputs IS0 through IS2, the comparator CMP causes its output E to go "LOW".
When the output E of the comparator CMP has a "HIGH" level and the interrupt request input A has a "HIGH" level, the AND gate G50 furnishes an output at a "HIGH" level and the selector SLT then furnishes the 3-bit output composed of the three bits LV0 through LV2 of the level number register LR and the 3-bit output composed of the three bits CN0 through CN2 of the identification number register NR as its outputs OS0 through OS2 and ON0 through ON2. Otherwise, the AND gate G50 furnishes an output at a "LOW" level and the selector SLT then furnishes the 3-bit input composed of the three bits IS0 through IS2 and the other 3-bit input composed of the three bits IN0 through IN2 as its outputs OS0 through OS2 and ON0 through ON2.
In other words, the interrupt handling element as shown in FIG. 10 furnishes the outputs LV0 through LV2 of the level number register LR and the outputs CN0 through CN2 of the identification number register NR as its outputs OS0 through OS2 and ON0 through ON2, respectively, when the interrupt request input A has a "HIGH" level and the interrupt level number designated by the outputs LV0 through LV2 of the level number register is greater than another interrupt level number designated by the three inputs IS0 through IS2. On the other hand, when the interrupt request input A has a "LOW" level or the interrupt level number designated by the outputs LV0 through LV2 of the level number register is equal to or less than another interrupt level number designated by the inputs IS0 through IS2, the interrupt handling element furnishes the input signal composed of the three bits IS0 through IS2 and the other input signal composed of the three bits IN0 through IN2 as its outputs OS0 through OS2 and ON0 through ON2, respectively.
Thus, in the case that a plurality of interrupt handling elements IE10 through IE17 each having the structure as shown in FIG. 10 are cascaded as shown in FIG. 9, the interrupt handling element IE17 at the final stage furnishes both the interrupt level number and the identification number which are respectively stored in the level number register LR and identification number register NR of one interrupt handling element with the highest interrupt level or priority included among all interrupt handling elements each of which has received an interrupt request input A at a "HIGH" level, as its outputs S2 through S0 and N2 through N0, respectively.
In the prior art interrupt controller which is so constructed as mentioned above and which can receive eight different interrupt request signals respectively corresponding to eight different causes, a plurality of interrupt handling elements each provided with a comparator and a selector are cascaded and the comparator of each interrupt handling element needs four or five gates arranged between its input and output terminals and the selector of each interrupt handling element needs two or three gates arranged between its input and output terminals. The prior art interrupt controller thus needs 48 to 64 gates to generate and furnish an interrupt level number signal and an interrupt identification number signal from the plurality of interrupt request signals applied thereto. Therefore, a problem with the prior art interrupt controller is that it takes a long time for a change in each interrupt request signal to influence its outputs, i.e., both the interrupt level number signal and the interrupt identification number signal.
In the prior art interrupt controller, a change in each interrupt request signal can directly cause a change in the interrupt identification number signal. Some central processing units process the interrupt identification number signal after they process the interrupt level number signal. For example, if an interrupt request having the identification number 3 is made such a central processing unit accepts the interrupt request by processing the corresponding interrupt level number signal. After that, when the interrupt request signal makes a "HIGH" to "LOW" transition, the prior art interrupt controller causes the interrupt identification number signal to change so that it represents the identification number 0 before the CPU processes the interrupt identification number signal, if there is no other interrupt request. Another problem is thus that the central processing unit CPU realizes by mistake that an interrupt request with the identification number 0 has been made.